Because testing of large integrated circuits generally cannot include taking measurements at internal nodes of the circuit, testing is generally done by applying to the primary inputs of the circuit a test vector, which is a set of logic values designed to test for a particular fault, and observing the resulting logic values at the primary output of the circuit to decide whether the circuit is free of the fault. For testing high-performance sequential circuits, testing for most if not all possible faults may require that a long sequence of test vectors (a test set) be applied to the primary inputs, and in some instances that the sequence be repeated. The size of a test sequence is the number of test vectors in the sequence and the size of a test set is the number of vectors in all its required test sequences. Generally, the generation of a full test set can be a formidable task.
The need for testing has become an important factor in the design of high-performance integrated circuits. It is generally impractical to incorporate integrated circuits that have not been tested into complex systems that require a number of integrated circuits, all operating successfully, and to run the risk of failure of the system in the field because of one defective integrated circuit.
One solution for rendering high-performance sequential designs to be more easily testable has been to introduce hardware modifications, such as synthesis or design for testability. After these modifications, state of the art sequential test generators can be used to obtain tests that provide high fault coverage. However, these modifications typically entail area and performance penalties and this may conflict with the area and performance constraints of the design.
Additionally, recent work has shown that retiming transformations that are known to preserve functionality, also preserve testability with respect to a single stuck-at fault test set. Therefore, another approach to testing retimed circuits can be to generate a test set for the original design and use this test set for the retimed circuit.